High-performance computing platforms: current status and development trends
Authors
A.S. Antonov
I.V. Afanasyev
Vl.V. Voevodin
Keywords:
supercomputer
performance
efficiency
processor
Top500
parallelism
accelerator
interconnect
Abstract
This paper provides an overview of the current state of supercomputer technology. The review is done from different points of view — from the construction features of modern computing devices to the features of the architecture of large supercomputer complexes. This review includes descriptions of the most powerful supercomputers in the world and Russia since the early of 2021 as well as some less powerful systems that are interesting from other points of view. It also focuses on the development trends of the supercomputer industry and describes the most famous projects for building future exascale supercomputers.
A. S. Antonov, D. A. Nikitenko, and V. V. Voevodin, “Algo500 -- A New Approach to the Joint Analysis of Algorithms and Computers,” Lobachevskii J. Math. 41 (8), 1435-1443 (2020).doi 10.1134/S1995080220080041.
Vl. V. Voevodin and A. P. Kapitonova, Methods for Describing and Classifying Computing Systems Architectures (Mosk. Gos. Univ., Moscow, 1994) [in Russian].
V. V. Voevodin and Vl. V. Voevodin, The Parallel Computing (BHV-Petersburg, St. Petersburg, 2002) [in Russian].
Classification of Computing Systems Architectures | PARALLEL.RU -- Information and Analytical Center for Parallel Computing. https://parallel.ru/computers/taxonomy . Cited April 25, 2021.
M. J. Flynn, “Very High-Speed Computing Systems,” Proc. IEEE 54 (12), 1901-1909 (1966). doi 10.1109/PROC.1966.5273
M. J. Flynn, “Some Computer Organizations and Their Effectiveness,” IEEE Trans. Comput. 21 (9), 948-960 (1972). doi 10.1109/TC.1972.5009071
J. A. Fisher, P. Faraboschi, and C. Young, “VLIW Processors,” in Encyclopedia of Parallel Computing (Springer, Boston, 2011), pp. 2135-2142. doi 10.1007/978-0-387-09766-4_471.
I. V. Afanasyev, V. V. Voevodin, K. Komatsu, and H. Kobayashi, “VGL: A High-Performance Graph Processing Framework for the NEC SX-Aurora TSUBASA Vector Architecture,” J. Supercomput. (2021). doi 10.1007/s11227-020-03564-9.
O. E. Okonta, D. Ajani, A. A. Owolabi, et al., “Performance Evaluation of Hyper Threading Technology Architecture Using Microsoft Operating System Platform,” West Afr. J. Ind. Acad. Res. 15 (1), 52-67 (2015).
Y.-C. Wang, J.-K. Chen, B.-R. Li, “An Empirical Study of HPC Workloads on Huawei Kunpeng 916 Processor,” in Proc. IEEE 25th Int. Conf. on Parallel and Distributed Systems, Tianjin, China, December 4—6, 2019 (IEEE Press, New York, 2019), pp. 360-367, doi 10.1109/ICPADS47876.2019.00057.
E. Calore, A. Gabbana, S. F. Schifano, and R. Tripiccione, “ThunderX2 Performance and Energy-Efficiency for HPC Workloads,” Computation 8 (1), 1-17 (2020). doi 10.3390/computation8010020
K. Komatsu, S. Momose, Y. Isobe, et al., “Performance Evaluation of a Vector Supercomputer SX-Aurora TSUBASA,” in Proc. Int. Conf. for High Performance Computing, Networking, Storage, and Analysis, Dallas, USA, November 11-16, 2018 (IEEE Press, Piscataway, 2018), pp. 685-696. doi 10.1109/SC.2018.00057
T. Wang, Z. Su, Y. Xia, et al., “NovaCube: A Low Latency Torus-Based Network Architecture for Data Centers,” in Proc. Global Communications Conf., Austin, USA, December 8—12, 2014 (IEEE Press, New York, 2014), pp. 2252-2257, doi 10.1109/GLOCOM.2014.7037143
X. Yuan, “On Nonblocking Folded-Clos Networks in Computer Communication Environments,” in IEEE International Parallel & Distributed Processing Symposium. (IEEE Press, Anchorage, USA, 2011), pp. 188-196, doi 10.1109/IPDPS.2011.27
Butterfly Network: Wikipedia.
J. Kim, W. J. Dally, and D. Abts, “Flattened Butterfly: A Cost-Efficient Topology for High-Radix Networks,” ACM SIGARCH Computer Architecture News 35 (2) (2007). doi 10.1145/1273440.1250679.
Y. Ajima, T. Kawashima, T. Okamoto, et al., “The Tofu Interconnect D,” in Proc. IEEE Int. Conf. on Cluster Computing, Belfast, UK, September 10-13, 2018 (IEEE Press, New York, 2018), pp. 646-654, doi 10.1109/CLUSTER.2018.00090
Y. Ajima, T. Inoue, S. Hiramoto, and T. Shimizu, “Tofu: Interconnect for the K Computer,” Fujitsu Sci. Tech. J. 48 (3), 280—285 (2012).
K. Harms, T. Leggett, B. Allen, et al., “Theta: Rapid Installation and Acceptance of an XC40 KNL System,” Concurr. Comput. 30 (1) (2018). doi 10.1002/cpe.4336
D. Sensi, S. Girolamo, K. H. McMahon, et al., “An In-Depth Analysis of the Slingshot Interconnect,” in Proc. Int. Conf. for High Performance Computing, Networking, Storage and Analysis, Atlanta, USA, November 9-19, 2020 (IEEE Press, New York, 2020), pp. 481-494, doi 10.1109/SC41405.2020.00039
T. F. Ismagilov, A. S. Semyonov, and A. S. Simonov, “Results of Evaluation Testing of the Angara Domestic High-Speed Communication Network,” in Russian Supercomputing Days (Mosk. Gos. Univ., Moscow, 2016), pp. 626-639.
A. Simonov, I. Zhabin, E. Kushtanov, et al., “Angara Interconnect: Architecture and Performance Results,” Voprosy Kiberbezopasn., No. 4, 46-53 (2019).
Y. Ajima, S. Sumimoto, and T. Shimizu, “Tofu: A 6D Mesh/Torus Interconnect for Exascale Computers,” Computer 42 (11), 36-40 (2009). doi 10.1109/MC.2009.370
H. Fu, J. Liao, J. Yang, et al., “The Sunway TaihuLight Supercomputer: System and Applications,” Sci. China Inf. Sci. 59 (2016). doi 10.1007/s11432-016-5588-7.
V. Voevodin, A. Antonov, D. Nikitenko, et al., “Lomonosov-2: Petascale Supercomputing at Lomonosov Moscow State University,” in Contemporary High Performance Computing: from Petascale toward Exascale (CRC Press, Boca Raton, 2019), Vol. 3, pp. 305-330.
V. V. Voevodin, A. S. Antonov, D. A. Nikitenko, et al., “Supercomputer Lomonosov-2: Large Scale, Deep Monitoring and Fine Analytics for the User Community,” Supercomput. Front. Innov. 6 (2), 4-11 (2019). doi 10.14529/jsfi190201
D. E. Shaw, J. P. Grossman, J. A. Bank, et al., “Anton 2: Raising the Bar for Performance and Programmability in a Special-Purpose Molecular Dynamics Supercomputer,” in Proc. Int. Conf. for High Performance Computing, Networking, Storage, and Analysis, New Orleans, USA, November 16-21, 2014 (IEEE Press, Piscataway, 2014), pp. 41-53, doi 10.1109/SC.2014.9.
K. J. Barker, K. Davis, A. Hoisie, et al., “Entering the Petaflop Era: The Architecture and Performance of Roadrunner,” in Proc. 2008 ACM/IEEE Conference on Supercomputing, Austin, USA, November 15-21, 2008 (IEEE Press, Austin, 2008), pp. 1-11, doi 10.1109/SC.2008.5217926.1