An approach to the programming of supercomputers on the basis of multicore multithreaded chips
Keywords:
architecture of supercomputers based on multicore multithreaded chips
scalable parallel programs
efficiency of parallel computing
Abstract
An approach to the development of parallel programs adapted to the architecture of supercomputers is proposed on the basis of multicore multithreaded chips. This approach is directed to overcome the negative effect of memory latency on the efficiency of parallel programs and can be considered as a method to develop scalable parallel programs.
Section
Section 2. Programming
References
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